The present invention relates generally to insulated gate field effect transistors (IGFETS) such as metal oxide semiconductor FETs (MOSFETs), and more particularly to vertical double diffused MOSFETS (VDMOS).
A conventional IGFET is a unipolar transistor in which current flows from a source region, through a channel in a body region, to a drain region. The channel can be induced (in an enhancement type device) or removed (in a depletion type device) by means of an electrostatic field produced by charges on a nearby gate electrode. In a MOSFET device the gate electrode is insulated from the semiconductor surface by an oxide layer. The gate typically lies between source and drain electrodes (disposed, respectively, on the source and drain regions) on a planar surface of the semiconductor substrate.
In a VDMOS structure, the drain electrode is on the opposite semiconductor surface from the gate and source electrodes, (although the drain region itself typically extends through the semiconductor, from an area adjacent to the body region on the first surface, to the drain electrode on the second surface). In VDMOS operation the channel occurs in the body region near the gate electrode (on the first surface). Current flows essentially horizontally (parallel to the first surface), from the source, through the channel region in the body, to the drain region, and then vertically (perpendicular to the first surface) through the drain region to the drain electrode (on the second surface).
The source-drain breakdown voltage of such a device is inversely proportional to the charge carrier concentration (ie-dopant level) in the drain region. Therefore, to increase device breakdown voltage, that portion of the drain region which is adjacent to the body region generally comprises lower conductivity semiconductor material (i.e., containing fewer charge carriers) than the remaining portion of the drain region. However, this has the detrimental effect of increasing the device turn-on resistance, because the conductivity of the region through which the charge carriers must travel is relatively low. The present invention is directed towards minimizing the resistance of the VDMOS drain region in selected areas so as to enhance device turn-on without degrading other device parameters, such as breakdown voltage.